1. Field of Invention
The present invention relates to a fabrication method for a semiconductor device. More particularly, the present invention relates to a method for fabricating shallow trench isolation (STI).
2. Description of Related Art
A complete circuit, such as an integrated circuit (IC) is usually composed of thousands of transistors. To prevent a short circuit between two adjacent transistors, an isolation region, known as a field oxide (FOX) layer, is added as isolation between the adjacent transistors, and such isolation is achieved through a local oxidation (LOCOS) process. However, there are several shortcomings associated with the LOCOS process, including related problems produced as a result of conventional stress, formation of a bird's beak around the LOCOS field isolation structure, and so on. In particular, the problem related to formation of the bird's beak has made the LOCOS field isolation structure an ineffective isolation on a smaller device.
A common method for isolating the device involves forming a conventional STI, in which a steep shallow trench is formed in a semiconductor substrate by anisotropic etching, with a silicon nitride layer serving as a hard mask. The shallow trench is then filled with an oxide layer, followed by performing chemical mechanical polishing (CMP) to planarize the oxide layer, so as to form a STI serving as an isolation region of the device. As a result, the problem regarding the formation of the bird's beak around the LOCOS field isolation structure is improved. Therefore, this is a preferred and scaleable isolation structure in the present process technology where higher integration is demanded together with a smaller line width.
Reference is made to FIG. 1A to Fig. 1C, in which fabricating steps for a conventional STI are illustrated in schematic, cross-sectional diagrams. Referring to FIG. 1A, a substrate 100 is provided with a pad oxide layer 102 and a mask layer 104 formed thereon, wherein the pad oxide layer 102 and the mask layer 104 are patterned to form a shallow trench 106 in the substrate 100.
Referring to FIG. 1B, the shallow trench 106 is filled with an insulating layer so as to form a STI 110 before performing a densification step.
Referring to FIG. 1C, the mask layer 104 and the pad oxide layer 102 are removed in sequence, followed by cleaning with a HF solution to complete the STI process.
As the substrate 100 is cleaned with the HF solution, a top corner 114 of the STI 110 is removed to form a recess 112. The recess 112 is then filled with a conducting layer (not shown), while the top corner 114 of the STI 110 is wrapped around by the conducting layer when the conducting layer is formed subsequently on the substrate 100. This causes a parasitic transistor conduction, which leads to an irregularity in a relationship graph of drain current (I.sub.d) versus gate voltage (V.sub.g) from the transistor that is formed above the STI. This irregularity is a hump in the graph of I.sub.d versus V.sub.g, causing an electron drift in the transistor.
To solve the above problem, an ion implantation step is conventionally performed on the exposed substrate in the shallow trench, after formation of the shallow trench, so that a doped region is formed on the exposed substrate to suppress the parasitic transistor conduction effect. A STI 210 formed as a result is shown in FIG. 2. However, an increase in the doping concentration for the substrate 200 increases the threshold voltage (V.sub.t) of the subsequently formed transistor and decreases its driving current. In addition, a higher doping concentration for the substrate 200 increases the junction electric field of a source/drain (S/D) region. As a result, a larger junction leakage current is produced between a doped region 216 at the edge of the STI 210 and the S/D region. Thus, the refresh time of the DRAM is degraded.